Relay_latching_DK1a1b (vsn. 27 July 2009 17:35)
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Type Panasonic DK1a1b Specification can be found here :-
http://pewa.panasonic.com/pcsd/product/pwr/pdf_cat/dk.pdf

1) WARNING.
It has been discovered that LTspice uses 'look-ahead' to simulate the operation of two cross coupled ('flip flop') basic AND gates. This results in the outputs changing state up to 12 mS BEFORE the 'set' / 'reset' inputs !!!
This makes it impossible to build a functional flip-flop out of (N)AND gates (even adding R-C delays in the feedback path does not prevent the output levels changing before the inputs) and suggests that LTspices' simulation of logic gates CAN  NOT BE TRUSTED. None are used in this sub-circuit.


2) To use this sub-assembly (which is not a .SUBCKT) both the Relay_latching_DK1a1b ".asc" and ".asy" files MUST be in the same folder as the Schematic in which you intend to use it.

You can then add the sub-assembly to your own Schematic by using the 'add symbol' command (set 'top directory' to the location of your schematic in order to 'see' the circuit ).

3) Coil resistance and Vthreshold has been set for the 3v unit = for other voltage ratings it is only necessary to change the coil resistance (R1 & R2) and the 'pull in' threshold voltage Vt (10 * threshold) settings.

4) The swirtching logic is based on 'voltage differences' between on1+ and on2+ .. so the circuit can be easily modified to simulate the rest of the DK range.

Although the Relay specification sheets define on1 & 2 as '+' and coil common as '-', there seems to be no reason why the relay should not function 'in reverse' (i.e. if coil common is '+' and on1 &on2 are driven '-', then on1- will enable in2<>out2 and on2- will enable in1<>out1). This circuit permits that.

5) The reason for using 10 times the differences (and hence 10* threshold) is to ensure the R-C delay voltage will always rise above the diode threshold trigger point (0.5v).

D1 (& D2) compensates for effect of D10 (& D20) and can be dispensed with if Vthreshold is adjusted instead.

D10 and D20 ensure that a negative 'reverse' difference does not 'bias' the delay time cct. prior to the arrival of a 'forward' onN+ pulse.

DD1 & DD2 are vital to prevent the delay caps (Cd1 & 2) 'running away' to 10* Vdiff  = if that happens, the discharge resistors Rd1 & 2 are unable to discharge the caps fast enough to allow the relay to switch when one onN+ pulse follows one another at high speed. Rd can be adjusted for the switching 'recovery time'.

6) The output stage is taken off one 'arm' of the 'state flip flop'. This is to ensure that the two switches are ALWAYS 'opposing' no matter what the flip flip is doing (earlier simulations resulted in both 'on' :-) ). Note, however, that Switch 'off' should be faster than 'on' (when switching occurs, both switches should be 'off' for approx 1mS before one ends in the 'on' state).





